93 lines
3.5 KiB
C
93 lines
3.5 KiB
C
/*
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Copyright 2018 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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sr_exp_t sr_exp_data;
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void SR_EXP_WriteData(void) {
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SR_EXP_RCLK_LO;
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while (!(SR_EXP_SERCOM->SPI.INTFLAG.bit.DRE)) {
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DBGC(DC_SPI_WRITE_DRE);
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}
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SR_EXP_SERCOM->SPI.DATA.bit.DATA = sr_exp_data.reg & 0xFF; // Shift in bits 7-0
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while (!(SR_EXP_SERCOM->SPI.INTFLAG.bit.TXC)) {
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DBGC(DC_SPI_WRITE_TXC_1);
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}
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SR_EXP_SERCOM->SPI.DATA.bit.DATA = (sr_exp_data.reg >> 8) & 0xFF; // Shift in bits 15-8
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while (!(SR_EXP_SERCOM->SPI.INTFLAG.bit.TXC)) {
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DBGC(DC_SPI_WRITE_TXC_2);
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}
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SR_EXP_RCLK_HI;
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}
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void SR_EXP_Init(void) {
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DBGC(DC_SPI_INIT_BEGIN);
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CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
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// Set up MCU Shift Register pins
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PORT->Group[SR_EXP_RCLK_PORT].DIRSET.reg = (1 << SR_EXP_RCLK_PIN);
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PORT->Group[SR_EXP_OE_N_PORT].DIRSET.reg = (1 << SR_EXP_OE_N_PIN);
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// Set up MCU SPI pins
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PORT->Group[SR_EXP_DATAOUT_PORT].PMUX[SR_EXP_DATAOUT_PIN / 2].bit.SR_EXP_DATAOUT_MUX_SEL = SR_EXP_DATAOUT_MUX; // MUX select for sercom
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PORT->Group[SR_EXP_SCLK_PORT].PMUX[SR_EXP_SCLK_PIN / 2].bit.SR_EXP_SCLK_MUX_SEL = SR_EXP_SCLK_MUX; // MUX select for sercom
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PORT->Group[SR_EXP_DATAOUT_PORT].PINCFG[SR_EXP_DATAOUT_PIN].bit.PMUXEN = 1; // MUX Enable
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PORT->Group[SR_EXP_SCLK_PORT].PINCFG[SR_EXP_SCLK_PIN].bit.PMUXEN = 1; // MUX Enable
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// Initialize Shift Register
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SR_EXP_OE_N_DIS;
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SR_EXP_RCLK_HI;
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SR_EXP_SERCOM->SPI.CTRLA.bit.DORD = 1; // Data Order - LSB is transferred first
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SR_EXP_SERCOM->SPI.CTRLA.bit.CPOL = 1; // Clock Polarity - SCK high when idle. Leading edge of cycle is falling. Trailing rising.
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SR_EXP_SERCOM->SPI.CTRLA.bit.CPHA = 1; // Clock Phase - Leading Edge Falling, change, Trailing Edge - Rising, sample
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SR_EXP_SERCOM->SPI.CTRLA.bit.DIPO = 3; // Data In Pinout - SERCOM PAD[3] is used as data input (Configure away from DOPO. Not using input.)
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SR_EXP_SERCOM->SPI.CTRLA.bit.DOPO = 0; // Data Output PAD[0], Serial Clock PAD[1]
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SR_EXP_SERCOM->SPI.CTRLA.bit.MODE = 3; // Operating Mode - Master operation
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SR_EXP_SERCOM->SPI.CTRLA.bit.ENABLE = 1; // Enable - Peripheral is enabled or being enabled
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while (SR_EXP_SERCOM->SPI.SYNCBUSY.bit.ENABLE) {
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DBGC(DC_SPI_SYNC_ENABLING);
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}
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sr_exp_data.reg = 0;
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sr_exp_data.bit.HUB_CONNECT = 0;
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sr_exp_data.bit.HUB_RESET_N = 0;
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sr_exp_data.bit.S_UP = 0;
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sr_exp_data.bit.E_UP_N = 1;
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sr_exp_data.bit.S_DN1 = 1;
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sr_exp_data.bit.E_DN1_N = 1;
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sr_exp_data.bit.E_VBUS_1 = 0;
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sr_exp_data.bit.E_VBUS_2 = 0;
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sr_exp_data.bit.SRC_1 = 1;
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sr_exp_data.bit.SRC_2 = 1;
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sr_exp_data.bit.IRST = 1;
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sr_exp_data.bit.SDB_N = 0;
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SR_EXP_WriteData();
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// Enable Shift Register output
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SR_EXP_OE_N_ENA;
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DBGC(DC_SPI_INIT_COMPLETE);
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}
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