6e984a8b5e
Microsecond (us) delays are now handled by a busy wait loop according to MCU frequency. This replaces the system counter method which had an overhead of around 12us. TC5 device and supporting routines removed as it was the old us delay counter. wait_ms is now properly a macro to CLK_delay_ms. wait_us is now properly a macro to CLK_delay_us. Removed CLK_get_us as it has no use. All calls to CLK_get_ms() have been replaced by timer_read64() with corrected typing. All calls to CLK_delay_ms() have been replaced by wait_ms(). All calls to CLK_delay_us() have been replaced by wait_us() and timings verified or updated as needed after review on scope. Corrected typing of variables using 64bit ms timer readings if needed.
392 lines
13 KiB
C
392 lines
13 KiB
C
/*
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Copyright 2018 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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#include <string.h>
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volatile clk_t system_clks;
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volatile uint64_t ms_clk;
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uint32_t usec_delay_mult;
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#define USEC_DELAY_LOOP_CYCLES 3 //Sum of instruction cycles in us delay loop
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const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0,(uint32_t)SERCOM1,(uint32_t)SERCOM2,(uint32_t)SERCOM3,(uint32_t)SERCOM4,(uint32_t)SERCOM5};
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const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35};
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#define USE_DPLL_IND 0
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#define USE_DPLL_DEF GCLK_SOURCE_DPLL0
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void CLK_oscctrl_init(void)
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{
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Oscctrl *posctrl = OSCCTRL;
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Gclk *pgclk = GCLK;
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DBGC(DC_CLK_OSC_INIT_BEGIN);
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//default setup on por
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system_clks.freq_dfll = FREQ_DFLL_DEFAULT;
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system_clks.freq_gclk[0] = system_clks.freq_dfll;
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//configure and startup 16MHz xosc0
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posctrl->XOSCCTRL[0].bit.ENABLE = 0;
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posctrl->XOSCCTRL[0].bit.STARTUP = 0xD;
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posctrl->XOSCCTRL[0].bit.ENALC = 1;
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posctrl->XOSCCTRL[0].bit.IMULT = 5;
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posctrl->XOSCCTRL[0].bit.IPTAT = 3;
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posctrl->XOSCCTRL[0].bit.ONDEMAND = 0;
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posctrl->XOSCCTRL[0].bit.XTALEN = 1;
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posctrl->XOSCCTRL[0].bit.ENABLE = 1;
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while (posctrl->STATUS.bit.XOSCRDY0 == 0) { DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC); }
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system_clks.freq_xosc0 = FREQ_XOSC0;
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//configure and startup DPLL
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posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 0;
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while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); }
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posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; //select XOSC0 (16MHz)
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posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; //16 MHz / (2 * (7 + 1)) = 1 MHz
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posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; //1 MHz * (PLL_RATIO(47) + 1) = 48MHz
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while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); }
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posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ONDEMAND = 0;
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posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1;
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while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE); }
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while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK); }
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while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY); }
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system_clks.freq_dpll[0] = (system_clks.freq_xosc0 / 2 / (posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV + 1)) * (posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR + 1);
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//change gclk0 to DPLL
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pgclk->GENCTRL[GEN_DPLL0].bit.SRC = USE_DPLL_DEF;
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while (pgclk->SYNCBUSY.bit.GENCTRL0) { DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0); }
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system_clks.freq_gclk[0] = system_clks.freq_dpll[0];
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usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000);
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if (usec_delay_mult < 1) usec_delay_mult = 1; //Never allow a multiplier of zero
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DBGC(DC_CLK_OSC_INIT_COMPLETE);
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}
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//configure for 1MHz (1 usec timebase)
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//call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
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uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq)
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{
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Gclk *pgclk = GCLK;
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DBGC(DC_CLK_SET_GCLK_FREQ_BEGIN);
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1); }
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pgclk->GENCTRL[gclkn].bit.SRC = USE_DPLL_DEF;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2); }
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pgclk->GENCTRL[gclkn].bit.DIV = (uint8_t)(system_clks.freq_dpll[0] / freq);
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3); }
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pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4); }
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pgclk->GENCTRL[gclkn].bit.GENEN = 1;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5); }
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system_clks.freq_gclk[gclkn] = system_clks.freq_dpll[0] / pgclk->GENCTRL[gclkn].bit.DIV;
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DBGC(DC_CLK_SET_GCLK_FREQ_COMPLETE);
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return system_clks.freq_gclk[gclkn];
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}
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void CLK_init_osc(void)
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{
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uint8_t gclkn = GEN_OSC0;
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Gclk *pgclk = GCLK;
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DBGC(DC_CLK_INIT_OSC_BEGIN);
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_1); }
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pgclk->GENCTRL[gclkn].bit.SRC = GCLK_SOURCE_XOSC0;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_2); }
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pgclk->GENCTRL[gclkn].bit.DIV = 1;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_3); }
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pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_4); }
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pgclk->GENCTRL[gclkn].bit.GENEN = 1;
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while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_5); }
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system_clks.freq_gclk[gclkn] = system_clks.freq_xosc0;
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DBGC(DC_CLK_INIT_OSC_COMPLETE);
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}
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void CLK_reset_time(void)
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{
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Tc *ptc4 = TC4;
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Tc *ptc0 = TC0;
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ms_clk = 0;
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DBGC(DC_CLK_RESET_TIME_BEGIN);
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//stop counters
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ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
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while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {}
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ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
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while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {}
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//zero counters
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ptc4->COUNT16.COUNT.reg = 0;
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while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) {}
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ptc0->COUNT32.COUNT.reg = 0;
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while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) {}
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//start counters
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ptc0->COUNT32.CTRLA.bit.ENABLE = 1;
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while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {}
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ptc4->COUNT16.CTRLA.bit.ENABLE = 1;
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while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {}
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DBGC(DC_CLK_RESET_TIME_COMPLETE);
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}
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void TC4_Handler()
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{
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if (TC4->COUNT16.INTFLAG.bit.MC0)
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{
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TC4->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0;
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ms_clk++;
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}
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}
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uint32_t CLK_enable_timebase(void)
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{
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Gclk *pgclk = GCLK;
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Mclk *pmclk = MCLK;
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Tc *ptc4 = TC4;
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Tc *ptc0 = TC0;
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Evsys *pevsys = EVSYS;
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DBGC(DC_CLK_ENABLE_TIMEBASE_BEGIN);
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//gclk2 highspeed time base
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CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
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CLK_init_osc();
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//unmask TC4, sourcegclk2 to TC4
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pmclk->APBCMASK.bit.TC4_ = 1;
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pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45;
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pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1;
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//configure TC4
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DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN);
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ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
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while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE); }
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ptc4->COUNT16.CTRLA.bit.SWRST = 1;
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while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1); }
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while (ptc4->COUNT16.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2); }
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//CTRLA defaults
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//CTRLB as default, counting up
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ptc4->COUNT16.CTRLBCLR.reg = 5;
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while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB); }
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ptc4->COUNT16.CC[0].reg = 999;
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while (ptc4->COUNT16.SYNCBUSY.bit.CC0) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0); }
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//ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1;
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//wave mode
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ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; //MFRQ match frequency mode, toggle each CC match
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//generate event for next stage
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ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1;
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NVIC_EnableIRQ(TC4_IRQn);
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ptc4->COUNT16.INTENSET.bit.MC0 = 1;
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DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE);
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//unmask TC0,1, sourcegclk2 to TC0,1
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pmclk->APBAMASK.bit.TC0_ = 1;
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pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45;
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pgclk->PCHCTRL[TC0_GCLK_ID].bit.CHEN = 1;
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pmclk->APBAMASK.bit.TC1_ = 1;
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pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45;
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pgclk->PCHCTRL[TC1_GCLK_ID].bit.CHEN = 1;
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//configure TC0
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DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN);
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ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
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while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE); }
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ptc0->COUNT32.CTRLA.bit.SWRST = 1;
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while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1); }
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while (ptc0->COUNT32.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); }
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//CTRLA as default
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ptc0->COUNT32.CTRLA.bit.MODE = 2; //32 bit mode
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ptc0->COUNT32.EVCTRL.bit.TCEI = 1; //enable incoming events
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ptc0->COUNT32.EVCTRL.bit.EVACT = 2 ; //count events
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DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE);
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DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN);
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//configure event system
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pmclk->APBBMASK.bit.EVSYS_ = 1;
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pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45;
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pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1;
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pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; //TC0 will get event channel 0
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pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; //Rising edge
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pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; //Synchronous
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pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; //TC4 MC0
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DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE);
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CLK_reset_time();
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ADC0_clock_init();
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DBGC(DC_CLK_ENABLE_TIMEBASE_COMPLETE);
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return 0;
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}
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void CLK_delay_us(uint32_t usec)
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{
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asm (
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"CBZ R0, return\n\t" //If usec == 0, branch to return label
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);
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asm (
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"MULS R0, %0\n\t" //Multiply R0(usec) by usec_delay_mult and store in R0
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".balign 16\n\t" //Ensure loop is aligned for fastest performance
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"loop: SUBS R0, #1\n\t" //Subtract 1 from R0 and update flags (1 cycle)
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"BNE loop\n\t" //Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles
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"return:\n\t" //Return label
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: //No output registers
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: "r" (usec_delay_mult) //For %0
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);
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//Note: BX LR generated
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}
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void CLK_delay_ms(uint64_t msec)
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{
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msec += timer_read64();
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while (msec > timer_read64()) {}
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}
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void clk_enable_sercom_apbmask(int sercomn)
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{
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Mclk *pmclk = MCLK;
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switch (sercomn)
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{
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case 0:
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pmclk->APBAMASK.bit.SERCOM0_ = 1;
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break;
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case 1:
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pmclk->APBAMASK.bit.SERCOM1_ = 1;
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break;
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case 2:
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pmclk->APBBMASK.bit.SERCOM2_ = 1;
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break;
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case 3:
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pmclk->APBBMASK.bit.SERCOM3_ = 1;
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break;
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default:
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break;
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}
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}
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//call CLK_oscctrl_init first
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//call CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
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uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq)
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{
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DBGC(DC_CLK_SET_SPI_FREQ_BEGIN);
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Gclk *pgclk = GCLK;
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Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
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clk_enable_sercom_apbmask(sercomn);
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//all gclk0 for now
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pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
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pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
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psercom->I2CM.CTRLA.bit.SWRST = 1;
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while (psercom->I2CM.SYNCBUSY.bit.SWRST) {}
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while (psercom->I2CM.CTRLA.bit.SWRST) {}
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psercom->SPI.BAUD.reg = (uint8_t) (system_clks.freq_gclk[0]/2/freq-1);
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system_clks.freq_spi = system_clks.freq_gclk[0]/2/(psercom->SPI.BAUD.reg+1);
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system_clks.freq_sercom[sercomn] = system_clks.freq_spi;
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DBGC(DC_CLK_SET_SPI_FREQ_COMPLETE);
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return system_clks.freq_spi;
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}
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//call CLK_oscctrl_init first
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//call CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT);
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uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq)
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{
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DBGC(DC_CLK_SET_I2C0_FREQ_BEGIN);
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Gclk *pgclk = GCLK;
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Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
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clk_enable_sercom_apbmask(sercomn);
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//all gclk0 for now
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pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
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pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
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psercom->I2CM.CTRLA.bit.SWRST = 1;
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while (psercom->I2CM.SYNCBUSY.bit.SWRST) {}
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while (psercom->I2CM.CTRLA.bit.SWRST) {}
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psercom->I2CM.BAUD.bit.BAUD = (uint8_t) (system_clks.freq_gclk[0]/2/freq-1);
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system_clks.freq_i2c0 = system_clks.freq_gclk[0]/2/(psercom->I2CM.BAUD.bit.BAUD+1);
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system_clks.freq_sercom[sercomn] = system_clks.freq_i2c0;
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DBGC(DC_CLK_SET_I2C0_FREQ_COMPLETE);
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return system_clks.freq_i2c0;
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}
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//call CLK_oscctrl_init first
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//call CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT);
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uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq)
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{
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DBGC(DC_CLK_SET_I2C1_FREQ_BEGIN);
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Gclk *pgclk = GCLK;
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Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
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clk_enable_sercom_apbmask(sercomn);
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//all gclk0 for now
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pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
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pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
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psercom->I2CM.CTRLA.bit.SWRST = 1;
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while (psercom->I2CM.SYNCBUSY.bit.SWRST) {}
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while (psercom->I2CM.CTRLA.bit.SWRST) {}
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|
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psercom->I2CM.BAUD.bit.BAUD = (uint8_t) (system_clks.freq_gclk[0]/2/freq-10);
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system_clks.freq_i2c1 = system_clks.freq_gclk[0]/2/(psercom->I2CM.BAUD.bit.BAUD+10);
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system_clks.freq_sercom[sercomn] = system_clks.freq_i2c1;
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|
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DBGC(DC_CLK_SET_I2C1_FREQ_COMPLETE);
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|
|
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return system_clks.freq_i2c1;
|
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}
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|
|
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void CLK_init(void)
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|
{
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|
DBGC(DC_CLK_INIT_BEGIN);
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|
|
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memset((void *)&system_clks,0,sizeof(system_clks));
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|
|
|
CLK_oscctrl_init();
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|
CLK_enable_timebase();
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|
|
|
DBGC(DC_CLK_INIT_COMPLETE);
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|
}
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|
|