91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
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/*
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Copyright 2018 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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Srdata_t srdata;
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void SPI_WriteSRData(void)
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{
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uint16_t timeout;
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SC2_RCLCK_LO;
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timeout = 50000;
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while (!(SCSPI->SPI.INTFLAG.bit.DRE) && --timeout) { DBGC(DC_SPI_WRITE_DRE); }
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SCSPI->SPI.DATA.bit.DATA = srdata.reg & 0xFF; //Shift in bits 7-0
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timeout = 50000;
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while (!(SCSPI->SPI.INTFLAG.bit.TXC) && --timeout) { DBGC(DC_SPI_WRITE_TXC_1); }
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SCSPI->SPI.DATA.bit.DATA = (srdata.reg >> 8) & 0xFF; //Shift in bits 15-8
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timeout = 50000;
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while (!(SCSPI->SPI.INTFLAG.bit.TXC) && --timeout) { DBGC(DC_SPI_WRITE_TXC_2); }
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SC2_RCLCK_HI;
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}
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void SPI_Init(void)
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{
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uint32_t timeout;
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DBGC(DC_SPI_INIT_BEGIN);
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CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
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PORT->Group[0].PMUX[6].bit.PMUXE = 2;
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PORT->Group[0].PMUX[6].bit.PMUXO = 2;
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PORT->Group[0].PINCFG[12].bit.PMUXEN = 1;
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PORT->Group[0].PINCFG[13].bit.PMUXEN = 1;
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//Configure Shift Registers
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SC2_DIRSET;
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SC2_RCLCK_HI;
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SC2_OE_DIS;
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SCSPI->SPI.CTRLA.bit.DORD = 1;
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SCSPI->SPI.CTRLA.bit.CPOL = 1;
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SCSPI->SPI.CTRLA.bit.CPHA = 1;
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SCSPI->SPI.CTRLA.bit.DIPO = 3;
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SCSPI->SPI.CTRLA.bit.MODE = 3; //master
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SCSPI->SPI.CTRLA.bit.ENABLE = 1;
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timeout = 50000;
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while (SCSPI->SPI.SYNCBUSY.bit.ENABLE && timeout--) { DBGC(DC_SPI_SYNC_ENABLING); }
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srdata.reg = 0;
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srdata.bit.HUB_CONNECT = 0;
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srdata.bit.HUB_RESET_N = 0;
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srdata.bit.S_UP = 0;
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srdata.bit.E_UP_N = 1;
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srdata.bit.S_DN1 = 1;
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srdata.bit.E_DN1_N = 1;
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srdata.bit.E_VBUS_1 = 0;
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srdata.bit.E_VBUS_2 = 0;
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srdata.bit.SRC_1 = 1;
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srdata.bit.SRC_2 = 1;
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srdata.bit.IRST = 1;
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srdata.bit.SDB_N = 0;
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SPI_WriteSRData();
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//Enable register output
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SC2_OE_ENA;
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DBGC(DC_SPI_INIT_COMPLETE);
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}
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